The memory capacity of a semiconductor memory device represented by a DRAM (Dynamic Random Access Memory) has increased every year. Along with this, proper selection of a chip floor plan has become important from cost and characteristic viewpoints. The “floor plan” means a total layout on a chip, such as the layout of plural memory cell arrays and peripheral circuits, the layout of data input/output pad strings (DQ pad strings), and the layout of data input/output buses (I/O buses).
Elements that determine the floor plan of a chip are circuit characteristics and a chip area required, and constraints at the module mounting. The floor plan needs to be determined by taking these elements into consideration. Focusing attention on the circuit characteristic out of these elements, it is preferable to suppress a difference between far and near ends, by setting a planar shape of a chip to substantially square. The chip having a substantially square planar shape can be easily employed in a semiconductor memory device having a four-bank structure that has conventionally been a main trend. In other words, in the four-bank structure, these banks can be laid out in two columns and in two rows.
However, a recent product having a large memory capacity, particularly a memory capacity equal to or larger than one Gbits, has a structure of eight or more banks in many cases. When a product has eight banks, for example, these banks are usually laid out in two columns and four rows, as a floor plan. In this case, a difference in the horizontal to vertical ratio of the chip becomes large, thereby increasing the difference between far and near ends.
On the other hand, in the chip of eight-bank structure, there is also known a floor plan having these banks laid out in three columns and three rows, with peripheral circuits laid out in concentration at the center (see Japanese Patent Applications Laid-open Nos. 2002-230976 and 2003-100073). However, in the floor plan having the peripheral circuits laid out in concentration at the center, the layouts of the DQ pad strings and the I/O buses easily give a large influence to the circuit characteristic. Therefore, the floor plan including the layouts of the DQ pad strings and the I/O buses needs to be selected more carefully.
Particularly, according to the common semiconductor memory device, the input/output data width, that is, the number of data bits simultaneously input or output, is variable, and the input/output data width can be selected by a fuse option method or a bonding option method. In this case, according to the floor plan of laying out the peripheral circuits in concentration at the center, the characteristics change easily depending on the selected input/output data width.